ARMV4_5_MRC - syntax, references, description

References

Location	Text
arm_opcodes.h:186	#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
aarch64.c:1061	instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
aarch64.c:2109	retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
aarch64.c:2216	ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
aarch64.c:2474	ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
arm11.c:197	ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
arm720t.c:435	ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
arm920t.c:1194	ARMV4_5_MRC(15, 0, 0, 10, 0, 0), ARMV4_5_LDR(1, 0));
arm920t.c:1300	ARMV4_5_MRC(15, 0, 0, 10, 0, 1), ARMV4_5_LDR(1, 0));
arm920t.c:1530	ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
arm_dpm.c:59	ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
arm_dpm.c:286	ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
arm_dpm.c:322	ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
arm_semihosting.c:199	ARMV4_5_MRC(15, 0, 0, 12, 0, 0),
armv7a.c:47	ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
armv7a.c:53	ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
armv7a.c:60	ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
armv7a.c:66	ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
armv7a.c:94	ARMV4_5_MRC(15, 0, 0, 0, 0, 0),
armv7a.c:132	ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
armv7a.c:146	ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx),
armv7a.c:293	ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
armv7a.c:336	ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
armv7a.c:383	ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
armv7a.c:396	ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
armv7a.c:407	ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
armv7a.c:467	ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
armv7a_mmu.c:47	ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
armv8.c:157	ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
armv8.c:638	ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
armv8.c:643	ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
armv8.c:741	ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value);
armv8.c:745	ARMV4_5_MRC(14, 0, 13, 0, 5, 0), value);
armv8.c:759	ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
armv8.c:769	ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
armv8.c:830	ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
armv8.c:848	ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
armv8.c:983	ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
armv8.c:989	ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
armv8.c:996	ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
armv8.c:1002	ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
armv8_dpm.c:501	ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
armv8_opcodes.c:47	[READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
armv8_opcodes.c:48	[READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
armv8_opcodes.c:49	[READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
armv8_opcodes.c:50	[READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
armv8_opcodes.c:52	[READ_REG_MPIDR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
armv8_opcodes.c:53	[READ_REG_DTRRX] = ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
armv8_opcodes.h:111	#define ARMV8_MRC_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MRC(cp, opc1, rt, crn, crm, opc2)
cortex_a.c:388	ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
cortex_a.c:437	ARMV4_5_MRC(14, 0, rt, 0, 5, 0),
cortex_a.c:2049	retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar, dscr);
cortex_a.c:2055	retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr, dscr);
cortex_a.c:2076	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr);
cortex_a.c:2180	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr);
cortex_a.c:2294	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
cortex_a.c:2388	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
cortex_a.c:2611	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
cortex_a.c:2694	retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
feroceon.c:372	arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, crn, crm, op2), 0, NULL, 0);

ARMV4_5_MRC macro

Syntax

Arguments

cp

op1

rd

crn

crm

op2

References