ARMV4_5_MCR - syntax, references, description

References

Location	Text
arm_opcodes.h:209	#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
aarch64.c:97	instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
aarch64.c:180	instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
aarch64.c:2303	retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
aarch64.c:2355	retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
arm720t.c:452	ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
arm920t.c:634	ARMV4_5_MCR(15, 0, 0, 7, 10, 4),
arm920t.c:678	ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0,
arm920t.c:711	ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
arm920t.c:720	ARMV4_5_MCR(15, 0, 0, 7, 5, 0),
arm920t.c:921	ARMV4_5_MCR(15, 2, 0, 15, 6, 2), ARMV4_5_LDR(1, 0));
arm920t.c:946	ARMV4_5_MCR(15, 0, 0, 9, 1, 0), ARMV4_5_LDR(1, 0));
arm920t.c:950	ARMV4_5_MCR(15, 2, 0, 15, 10, 2),
arm920t.c:955	ARMV4_5_MCR(15, 2, 0, 15, 6, 2),
arm920t.c:994	ARMV4_5_MCR(15, 0, 0, 9, 1, 0), ARMV4_5_LDR(1, 0));
arm920t.c:1022	ARMV4_5_MCR(15, 2, 0, 15, 5, 2), ARMV4_5_LDR(1, 0));
arm920t.c:1047	ARMV4_5_MCR(15, 0, 0, 9, 1, 1), ARMV4_5_LDR(1, 0));
arm920t.c:1051	ARMV4_5_MCR(15, 2, 0, 15, 9, 2),
arm920t.c:1056	ARMV4_5_MCR(15, 2, 0, 15, 5, 2),
arm920t.c:1094	ARMV4_5_MCR(15, 0, 0, 9, 1, 1), ARMV4_5_LDR(1, 0));
arm920t.c:1221	ARMV4_5_MCR(15, 0, 0, 10, 0, 0),
arm920t.c:1226	ARMV4_5_MCR(15, 4, 0, 15, 6, 4),
arm920t.c:1258	ARMV4_5_MCR(15, 0, 0, 10, 0, 0), ARMV4_5_STR(1, 0));
arm920t.c:1262	ARMV4_5_MCR(15, 4, 0, 15, 10, 4), ARMV4_5_LDR(2, 0));
arm920t.c:1266	ARMV4_5_MCR(15, 4, 0, 15, 2, 5), ARMV4_5_LDR(3, 0));
arm920t.c:1289	ARMV4_5_MCR(15, 0, 0, 10, 0, 0), ARMV4_5_STR(1, 0));
arm920t.c:1327	ARMV4_5_MCR(15, 0, 0, 10, 0, 1),
arm920t.c:1332	ARMV4_5_MCR(15, 4, 0, 15, 5, 4),
arm920t.c:1364	ARMV4_5_MCR(15, 0, 0, 10, 0, 1), ARMV4_5_STR(1, 0));
arm920t.c:1368	ARMV4_5_MCR(15, 4, 0, 15, 9, 4), ARMV4_5_LDR(2, 0));
arm920t.c:1372	ARMV4_5_MCR(15, 4, 0, 15, 1, 5), ARMV4_5_LDR(3, 0));
arm920t.c:1395	ARMV4_5_MCR(15, 0, 0, 10, 0, 1), ARMV4_5_STR(1, 0));
arm920t.c:1546	ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
arm_dpm.c:107	ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
arm_dpm.c:188	ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
arm_dpm.c:218	ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
armv7a.c:330	ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
armv7a_cache.c:73	ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
armv7a_cache.c:171	ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
armv7a_cache.c:182	ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_end);
armv7a_cache.c:192	ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
armv7a_cache.c:236	ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
armv7a_cache.c:280	ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
armv7a_cache.c:315	ARMV4_5_MCR(15, 0, 0, 7, 1, 0), 0);
armv7a_cache.c:319	ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0);
armv7a_cache.c:362	ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line);
armv7a_cache.c:367	ARMV4_5_MCR(15, 0, 0, 7, 5, 7), va_line);
armv7a_mmu.c:42	ARMV4_5_MCR(15, 0, 0, 7, 8, 0),
armv8.c:603	ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
armv8.c:608	ARMV4_5_MCR(14, 0, 13, 0, 5, 0),
armv8.c:623	ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
armv8.c:633	ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
armv8.c:702	ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
armv8.c:717	ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
armv8.c:774	ARMV4_5_MCR(15, 0, 0, 5, 0, 0),
armv8.c:779	ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
armv8_dpm.c:526	ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
armv8_opcodes.c:51	[WRITE_REG_CSSELR] = ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
armv8_opcodes.c:54	[WRITE_REG_DTRTX] = ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
armv8_opcodes.c:61	[ARMV8_OPC_DCCISW] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
armv8_opcodes.c:62	[ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
armv8_opcodes.c:63	[ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
armv8_opcodes.h:110	#define ARMV8_MCR_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MCR(cp, opc1, rt, crn, crm, opc2)
cortex_a.c:490	ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
cortex_a.c:524	ARMV4_5_MCR(14, 0, rt, 0, 5, 0),
cortex_a.c:2021	retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr);
cortex_a.c:2101	retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar, dscr);
cortex_a.c:2105	retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr, dscr);
cortex_a.c:2437	retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr);
feroceon.c:402	arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, crn, crm, op2), 0, NULL, 0);

ARMV4_5_MCR macro

Syntax

Arguments

cp

op1

rd

crn

crm

op2

References