| Location | Text |
|---|
![]() arm_adi_v5.c:1003 | ![]( "Declaration") #define ARCH_ID(architect, archid) ( \ |
![]() arm_adi_v5.c:1013 | { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" }, |
![]() arm_adi_v5.c:1014 | { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" }, |
![]() arm_adi_v5.c:1015 | { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" }, |
![]() arm_adi_v5.c:1016 | { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" }, |
![]() arm_adi_v5.c:1017 | { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" }, |
![]() arm_adi_v5.c:1018 | { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" }, |
![]() arm_adi_v5.c:1019 | { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" }, |
![]() arm_adi_v5.c:1020 | { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" }, |
![]() arm_adi_v5.c:1021 | { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" }, |
![]() arm_adi_v5.c:1022 | { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" }, |
![]() arm_adi_v5.c:1023 | { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" }, |
![]() arm_adi_v5.c:1024 | { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" }, |
![]() arm_adi_v5.c:1025 | { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" }, |
![]() arm_adi_v5.c:1026 | { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" }, |
![]() arm_adi_v5.c:1027 | { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" }, |
![]() arm_adi_v5.c:1028 | { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" }, |
![]() arm_adi_v5.c:1029 | { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" }, |
![]() arm_adi_v5.c:1030 | { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" }, |
![]() arm_adi_v5.c:1031 | { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" }, |
![]() arm_adi_v5.c:1032 | { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" }, |
![]() arm_adi_v5.c:1033 | { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" }, |
![]() arm_adi_v5.c:1034 | { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" }, |
![]() arm_adi_v5.c:1038 | |
![]() arm_adi_v5.c:1039 | |
![]() arm_adi_v5.c:1040 | |