simulate_entity(EntityName);
Every time a simulator-targeted configuration is built all source files are scanned for
You don't have to write clock generation code every time! See the examples section for more details.
simulate_entity(MyTestbenchName);
If you want to use the same testbench in the simulator and on the FPGA, you can declare an entity with an input port called "clk" and use Core.SimulatedClockProvider as the testbench.
simulate_entity(SimulatedClockProvider<20ns, MyEntityWithClkInput>);
You can reuse clock generation code in your testbench by inheriting Core.SimulatedClockBase entity. E.g.:
entity MyTestbench : SimulatedClockBase<10ns>
{
LEDBlinkDemo uut(
clk = clk,
LEDs = auto
);
}
simulate_entity(MyTestbench);
By inheriting SimulatedClockBase the MyTestbench entity automatically receives a "clk" signal with the period specified as SimulatedClockBase template argument.