logic[] __bin(string value);
The Note that you can initialize vectors of size 32 and less with normal C++ style integral constants (e.g. 15, 0xF or 0b1111).
entity Test
{
signal auto xxx = __bin("010"), yyy = 0b010;
signal logic[4] xx2 = __bin("0010"), yy2 = 0b010;
}
Generated VHDL code:
signal xxx : std_logic_vector(2 downto 0) := B"010";
signal yyy : integer := 2;
signal xx2 : std_logic_vector(3 downto 0) := X"2";
signal yy2 : std_logic_vector(3 downto 0) := X"2";