TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 16.9.4

BIOS Version: bios_6_52_00_11_eng

XDCTools Version: xdctools_3_50_03_33_core

Benchmark	Cycles
Interrupt Latency	126
Hwi_restore()	9
Hwi_disable()	13
Hwi dispatcher prolog	102
Hwi dispatcher epilog	237
Hwi dispatcher	333
Hardware Interrupt to Blocked Task	549
Hardware Interrupt to Software Interrupt	371
Swi_enable()	82
Swi_disable()	11
Post Software Interrupt Again	36
Post Software Interrupt without Context Switch	102
Post Software Interrupt with Context Switch	199
Create a New Task without Context Switch	2002
Set a Task Priority without a Context Switch	174
Task_yield()	216
Post Semaphore No Waiting Task	51
Post Semaphore No Task Switch	198
Post Semaphore with Task Switch	269
Pend on Semaphore No Context Switch	83
Pend on Semaphore with Task Switch	292
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	4068
POSIX Set a Task Priority without a Context Switch	236
POSIX Post Semaphore No Waiting Task	67
POSIX Post Semaphore No Task Switch	217
POSIX Post Semaphore with Task Switch	284
POSIX Pend on Semaphore No Context Switch	94
POSIX Pend on Semaphore with Task Switch	302

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.