IAR Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 8.11.1.47

BIOS Version: bios_6_52_00_11_eng

XDCTools Version: xdctools_3_50_03_33_core

Benchmark	Cycles
Interrupt Latency	140
Hwi_restore()	7
Hwi_disable()	9
Hwi dispatcher prolog	117
Hwi dispatcher epilog	216
Hwi dispatcher	323
Hardware Interrupt to Blocked Task	509
Hardware Interrupt to Software Interrupt	330
Swi_enable()	56
Swi_disable()	12
Post Software Interrupt Again	20
Post Software Interrupt without Context Switch	81
Post Software Interrupt with Context Switch	166
Create a New Task without Context Switch	1457
Set a Task Priority without a Context Switch	146
Task_yield()	217
Post Semaphore No Waiting Task	44
Post Semaphore No Task Switch	160
Post Semaphore with Task Switch	250
Pend on Semaphore No Context Switch	57
Pend on Semaphore with Task Switch	274
Clock_getTicks()	9
POSIX Create a New Task without Context Switch	2772
POSIX Set a Task Priority without a Context Switch	188
POSIX Post Semaphore No Waiting Task	57
POSIX Post Semaphore No Task Switch	172
POSIX Post Semaphore with Task Switch	256
POSIX Pend on Semaphore No Context Switch	47
POSIX Pend on Semaphore with Task Switch	281

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.