GCC Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC2650:1

Tool Chain Version: 6.3.1

BIOS Version: bios_6_52_00_11_eng

XDCTools Version: xdctools_3_50_03_33_core

Benchmark	Cycles
Interrupt Latency	191
Hwi_restore()	16
Hwi_disable()	16
Hwi dispatcher prolog	118
Hwi dispatcher epilog	204
Hwi dispatcher	313
Hardware Interrupt to Blocked Task	537
Hardware Interrupt to Software Interrupt	385
Swi_enable()	86
Swi_disable()	17
Post Software Interrupt Again	38
Post Software Interrupt without Context Switch	106
Post Software Interrupt with Context Switch	212
Create a New Task without Context Switch	4638
Set a Task Priority without a Context Switch	174
Task_yield()	213
Post Semaphore No Waiting Task	61
Post Semaphore No Task Switch	202
Post Semaphore with Task Switch	266
Pend on Semaphore No Context Switch	72
Pend on Semaphore with Task Switch	301
Clock_getTicks()	237
POSIX Create a New Task without Context Switch	7549
POSIX Set a Task Priority without a Context Switch	255
POSIX Post Semaphore No Waiting Task	75
POSIX Post Semaphore No Task Switch	217
POSIX Post Semaphore with Task Switch	280
POSIX Pend on Semaphore No Context Switch	86
POSIX Pend on Semaphore with Task Switch	316

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m3 -mthumb -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.