GCC Cortex-A9 with hard FP Timing Benchmarks

Target Platform: ti.platforms.sdp4430

Tool Chain Version: 6.3.1

BIOS Version: bios_6_52_00_11_eng

XDCTools Version: xdctools_3_50_03_33_core

Benchmark	Cycles
Interrupt Latency	319
Hwi_restore()	9
Hwi_disable()	5
Hwi dispatcher prolog	195
Hwi dispatcher epilog	167
Hwi dispatcher	366
Hardware Interrupt to Blocked Task	632
Hardware Interrupt to Software Interrupt	363
Swi_enable()	79
Swi_disable()	20
Post Software Interrupt Again	25
Post Software Interrupt without Context Switch	82
Post Software Interrupt with Context Switch	151
Create a New Task without Context Switch	2627
Set a Task Priority without a Context Switch	104
Task_yield()	262
Post Semaphore No Waiting Task	42
Post Semaphore No Task Switch	196
Post Semaphore with Task Switch	315
Pend on Semaphore No Context Switch	36
Pend on Semaphore with Task Switch	306
Clock_getTicks()	16
POSIX Create a New Task without Context Switch	5240
POSIX Set a Task Priority without a Context Switch	95
POSIX Post Semaphore No Waiting Task	45
POSIX Post Semaphore No Task Switch	199
POSIX Post Semaphore with Task Switch	342
POSIX Pend on Semaphore No Context Switch	44
POSIX Pend on Semaphore with Task Switch	314

As the timer used to run these benchmarks is run at 1/2 the CPU frequency, an deviation of +-2 cycles is to be expected.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.